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PowerFFT™ ASIC
The PowerFFT™ is the world's fastest and most powerful programmable FFT-centric floating-point DSP,
able to process 100 million complex samples per second in continuous mode, with a rich set of
functionalities for Fast-Fourier Transforms (FFT) computations and FFT-based algorithms, including
n-dimensional FFTs, correlations and convolutions. The PowerFFT™ is a mature ASIC, implemented in
numerous Defense, Security and other applications since 2002. The PowerFFT™ is deployed in the systems
and solutions EONIC supplies which come in various formfactors of Commercial Off-The-Shelf cPCI boards.
One-dimensional: The stand-alone PowerFFT™ processor executes sustained FFT processing,
vector-multiplication convolutions and correlations on 1-D complex data sets of 1K IEEE
floating-point samples. With EONIC's patented memory controller, the PowerFFT™ does sustained FFT
processing, vector multiplication convolutions and correlations on 1D complex data sets of more
than one million samples.
Multi-dimensional: The PowerFFT has four data ports for four SDRAM banks for long FFT processing or
multidimensional FFT-based processing. Port 0 is the 64 bit primary input port, Port 5 is the 64 bit
primary output port, and Ports 1 to 4 can be connected to SDRAM banks to handle no penalty corner-turn
operations or act as double buffers for intermediate results storage. The patented EONIC Memory
Controller performs zero-penalty multidimensional SDRAM addressing (including refresh if necessary),
providing external memory type independence to the PowerFFT™ (SRAM can also be used).
PowerFFT™ processor programming is done with its instruction set. The instructions determine the
data flow and the memory addresses to be generated by the addressing FPGA. Depending on the
user calls (one call can be, for example, the convolution of a 256 X 256 kernel with a 512 x 512 data set),
a proper instruction set is selected for the FFT chip.
Basically, one instruction contains the following information:
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mode of the FFT core / vector multiplier; length of the data vectors
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data transfer settings:
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target port of the input Port 0 data vector
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source port of the output Port 5 data vector
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source and target port of the vector to be processed
In this way, many FFT operations can be mapped on the PowerFFT™ processor by sequencing PowerFFT™ instructions. Basic instruction sets for representative operations, such as those listed in the benchmarks table here below, are preprogrammed. User/application-specific multidimensional FFT-based operations are implemented by downloading specific instruction sets.
Benchmarks
| 1k pts points FFT, including windowing | 10 µs |
| 1M points convolution or correlation, including windowing | 21 ms |
| 1k points convolution or correlation, fixed filter | 23 µs |
| 1k points convolution or correlation, updated filter | 33 µs |
| 1M points convolution or correlation, fixed filter | 42 ms |
| 1M points convolution or correlation, updated filter | 63 ms |
| 1K x 1K points 2D FFT, including windowing | 21 ms |
| 1K x 1K pts 2D convolution or correlation, fixed filter | 42 ms |
| 1K x 1K pts 2D convolution or correlation, updated filter | 63 ms |
These performance figures have been measured on the PowerFFT™ PCI-64 board during continuous execution
of FFT algorithms on complex IEEE floating-point data (2 x 32 bit) stored in external RAM, using
standard SDRAM banks, and including RAM access latency times in read and write operations.
No simulated data.
 
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